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Delphi Data Link Controller

The Delphi DLC is a custom IC which is an interface between a microcontroller and the SAE J1850 medium speed automotive communications bus. Specifically, this IC interfaces to J1850's 10.4KBaud, single wire, VPW protocol option. The port exchanges information with the microcontroller via either an 8-bit, non-multiplexed parallel data bus or a serial SPI port. This method of exchange is selectable depending on the state of an input pin. The part handles all necessary data buffering, filtering protocol conversion and bus arbitration activities as described in J1850. The part also has an on-board, single wire bus transceiver, which forms the interface to the J1850 bus. This interface transmits and receives 7V bus waveforms, is powered off 12V battery, and is tolerant of up to 2V of ground offset (between nodes). The IC will survive, and not pass along to the controller, transients of up to 40V on the Vbatt line. The transmitter waveshapes transitions on the bus in order to reduce radiated emissions on the J1850 bus.

Features

Parallel or serial (SPI) microcontroller interface (selected by state of input pin)
Uses 2, 4, 6, or 8MHz clock supplied through either a ceramic resonator or a square wave source
11-byte transmit FIFO *20-byte receive FIFO
Configurable for multiple interrupt types
Low-power sleep mode
On-board, low RFI, J1850 bus transceiver

Packaging

Available in 28-pin SOIC
Available in 28-pin PLCC

Typical Applications

Automotive Communications
Multiplexing

Recommended Operating Conditions

Characteristic	Symbol	Value	Unit
Supply Voltage	Vdd	4.75 to 5.25	V
Supply Voltage	Vcc	4.75 to 5.25	V
Supply Voltage	Vbatt	9 to 16	V
Operating Temp. Range, Ambient	Ta	-40 to 125	?C

Absolute Maximum Ratings

Characterictic	Symbol	Value	Unit
Supply Voltage	Vdd	-0.5 to 5.75	V
Supply Voltage	Vcc	-0.5 to 5.75	V
Supply Voltage	Vbatt	-0.5 to 26.5	V
Input Voltage	Vin	-0.5 to Vdd 0.5	V
Storage Temp. Range	Tstg	-65 to 150	?C
Max. Junction Temp.	?	150	?C

Electrical Performance Characteristics - DLC

Characteristics	Symbol	Condition	Min	Max	Unit
Continuous Power	Pcmax	7.8 KHz bus waveform (50% duty cycle); 4MHz resonator 16V battery		333	mW
Battery Sleep Current	lbatt, sleep	DLC in sleep mode	?	5	?A
Battery Current Draw	lbatt, sleep	7.8KHz bus waveform (50% duty cycle); 4MHz resonator 16V battery		50	mA
Oscillator Stabilization Time	Twkint	DLC previously in sleep state, the powered up		105	?S
Oscillator Feedback Resistance	Rf	Vcc=Vdd=5.25V	.05	10	Mohm
E-Clock Cycle Time	Tcyc	Parrallel Mode	238	?	nS
E-Clock Pulse Width Low	Twel	Parrallel Mode	105	?	nS
E-Clock Pulse Width High	Tweh	Parrallel Mode	100	?	nS
E-Clock RiseDFall Time	tr,f	Parrallel Mode	0	20	nS
Address select setup time	tassu	Parrallel Mode	20	?	nS
Chip select setup time	tcssu	Parrallel Mode	0	?	nS
RDW* setup time	trwsu	Parrallel Mode	25	?	nS
Data in setup time	tdsui	Parrallel Mode	45	?	nS
Data out valid time	tedv	Parrallel Mode		75	nS
Min. SCLK cycle time	Tcyc	Serial Mode	238	?	nS
Min. Clock high time	tskhi	Serial Mode	80	?	nS
Min. Clock low time	tsklo	Serial Mode	80	?	nS
Access Time	tacc	Serial Mode	?	60	nS
Data out delay	tpdo	Serial Mode	?	59	nS
Output High Volt.	Voh	Vdd=4.75 to 5.25V; loh=-200?A	Vdd-0.8	?	V
Output Low Volt.	Vol	Vdd=4.75 to 5.25V; lol=1.6mA	?	0.4	V
Input High Volt.	Vih	Vdd=4.75 to 5.25V; lin=10?A	.07*Vdd	?	V
Input Low Volt.	Vil	Vdd=4.75 to 5.25V; lin=10?A	?	0.8	V
Input Curr. Limits	lin	Vdd=4.75 to 5.25V; all inputs except OSCI, CS*	-10	10	?A
Input Curr. Limits	lih, osc 1	Vdd=4.75 to 5.25V; all inputs except OSCI, CS*	0.525	10.5	?A
Input Curr. Limits	lin,cs*	Vdd=4.75 to 5.25V; all inputs except OSCI, CS*	-600	50	?A
Output Leak. (Hi-Z)	loz	VOut to GND; Vdd=4.75 to 5.25V; DO-D7, INT*	-10	10	?A
Output High Volt.	Voh	100% bus utilization; 4MHz; Vbatt=9-26.5VDVbatt=7-9V	6.25D5.25	8D9	V
Transceiver Trip Pt.	Vt	?	3.875	?	V
Load Resistance	Rmin, node	Min. load res. introduced onto bus	1500	?	Ohms

Delphi Data Link Controller (52k)